1. Field
The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device having a multilayer interconnection structure and a method for manufacturing the same.
2. Description of the Related Art
In a present-day semiconductor integrated circuit device, a number of semiconductor elements are disposed on a common substrate and a multilayer interconnection structure is used for mutually connecting them.
In the multilayer interconnection structure, interlayer insulating films, in which an interconnection pattern for constituting an interconnection layer is embedded, are laminated. In the above-described multilayer interconnection structure, a lower interconnection layer and an upper interconnection layer are connected through a via contact disposed in the interlayer insulating film.
In particular, regarding a recent ultrafine, very high speed semiconductor device, a low dielectric constant film (so-called low-k film) is used as an interlayer insulating film in order to reduce a signal delay (RC delay:resister-capacitor delay) problem in the multilayer interconnection structure. In addition to this, a low resistance copper (Cu) pattern is used as an interconnection pattern.
Regarding the multilayer interconnection structure in which the Cu interconnection pattern is embedded in the low dielectric constant interlayer insulating film, as described above, since patterning of the Cu layer through dry etching is difficult, a so-called damascene process or dual damascene process is employed, in which an interconnection groove or a via hole is formed in the interlayer insulating film in advance. In the damascene process or the dual damascene process, the thus formed interconnection groove or via hole is filled with a Cu layer and, thereafter, an excess Cu layer on the interlayer insulating film is removed by chemical mechanical polishing (CMP).
At that time, if the Cu interconnection pattern contacts the interlayer insulating film directly, Cu atoms diffuse into the interlayer insulating film so as to cause a short-circuit problem and the like. Therefore, in general, the side wall surface and the bottom surface of the interconnection groove or the via hole, in which the Cu interconnection pattern is disposed, are covered with an electrically conductive diffusion barrier, i.e. a so-called barrier metal film, and a Cu layer is deposited on such a barrier metal film. As for the barrier metal film, generally, high melting point metals, e.g., tantalum (Ta), titanium (Ti), and tungsten (W), or electrically conductive nitrides of these high melting point metals are used.
On the other hand, regarding recent 45-nm-generation and later ultrafine, very high speed semiconductor devices, the sizes of the interconnection grooves or the via holes formed in the interlayer insulating films have been reduced significantly along with miniaturization.
Consequently, in the case where a desired reduction of interconnection resistance by using the above-described barrier metal film having a large resistivity is intended, it is necessary to minimize the film thickness of the barrier metal film formed in the fine interconnection groove or via hole.
On the other hand, it is necessary that the side wall surface and the bottom surface of the interconnection groove or the via hole are continuously covered with the barrier metal film.
Under such circumstances, in Japanese Laid-open Patent Publication No. 2003-218198, an interconnection groove or a via hole formed in an interlayer insulating film is covered directly with a copper manganese alloy layer (Cu—Mn alloy layer).
Japanese Laid-open Patent Publication No. 2003-218198 describes a technology of forming a manganese silicon oxide layer having a thickness of 2 nm to 3 nm and a composition of MnSixOy as a diffusion barrier film at an interface between the above-described Cu—Mn alloy layer and the interlayer insulating film through a self-organization reaction between Mn in the above-described Cu—Mn alloy layer and Si and oxygen in the interlayer insulating film.
However, regarding this technology, a problem is recognized in that the self-organized layer has a composition of MnSixOy, the concentration of metal element, i.e. manganese (Mn), contained in the film is low and, for this reason, the adhesion to the Cu film is insufficient.
Therefore, Japanese Laid-open Patent Publication No. 2007-27259 describes a barrier metal structure having a configuration in which a Cu—Mn alloy layer and a high melting point barrier metal, e.g., Ta and Ti, are combined.
The above-described barrier metal structure, in which the Cu—Mn alloy layer and the barrier metal film of the high melting point metal, e.g., Ta and Ti, are combined, has also a favorable feature in that the oxidation resistance is improved because of the circumstances described below.
In recent years, for the purpose of avoiding a signal delay, use of a porous low dielectric constant film as a low dielectric constant material constituting the interlayer insulating film has been proposed. However, there are problems in that such a porous low dielectric constant material has a low density and is susceptible to damage due to plasma during production. The surface and the inside of the damaged film adsorbs moisture easily. Consequently, a barrier metal film formed on this porous low dielectric constant film is easy to oxidize under the influence of moisture adsorbed in the porous dielectric film and the performance as a diffusion barrier and the adhesion to a Cu interconnection layer or a via plug easily deteriorates.
However, if the above-described Cu—Mn alloy layer is used as a seed layer in such a structure, Mn in the Cu—Mn alloy layer reacts with an oxidizable portion of the barrier metal film and, thereby, the performance as the diffusion barrier and high adhesion to the Cu interconnection layer or the via plug can be maintained.
By the way, in the case where the Cu interconnection layer is formed by an electroplating method, it is necessary that the seed layer is formed in such a way that the seed layer covers the side wall surface and the bottom surface of the interconnection groove or the via hole continuously. If the seed layer is discontinuous, a void may occur in the interconnection or the via plug during electroplating. In the case where such a seed layer is formed by a sputtering method, it is thought of that the seed layer having a sufficient film thickness is formed on the side wall surface and the bottom of the interconnection groove or the via hole through resputtering or the like and, thereby, the resulting seed layer reliably continuously cover the side wall surface of the interconnection groove or the via hole. However, if this method is employed, overhang of the seed layer formed on upper portion of the interconnection groove or the via hole becomes significant. If the overhang becomes significant, a margin for filling with electroplating conducted thereafter is reduced significantly, so that voids tend to occur during the electroplating.
On the other hand, as a result of miniaturization of the semiconductor device, the width of the interconnection groove or the diameter of the via hole is reduced. Along with this, film thickness reduction of the seed layer is required. However, in particular, insofar as the seed layer is formed by a sputtering method, it is very difficult to cover the side wall surface and the bottom surface of the interconnection groove or the via hole with a film having a sufficient thickness regarding particularly a highly miniaturized semiconductor device. Furthermore, in the case where a low-k material having a low modulus of elasticity is used as the interlayer insulating film, bowing may occur in a cross-sectional shape of the interconnection groove or the via hole after etching. In particular, regarding the side wall portion of the interconnection groove having a large surface area, even when the seed layer is a continuous film, the film thickness may be reduced locally as a result of fluctuation in the film thickness.
If the film thickness of the seed layer is reduced locally in the side wall portion of the interconnection groove, as described above, the above-described thin film portion of the above-described seed layer may be dissolved at an initial stage of a copper interconnection formation step by the electroplating method. In the case where an electroplating step is conducted by using such a partly dissolved seed layer, a problem may occur in that a void occurs at a place corresponding to the local thin film portion of the seed layer in a heat treatment step conducted thereafter.
An occurrence of void due to such a little dissolution of the seed layer is characterized in that in general, faulty filling is not observed just after plating, but a void occurs only after the heat treatment step is conducted. The reason for this is believed to be that the interconnection pattern itself is formed through a bottom-up fill mechanism in the electroplating, a Cu plating film is formed without void apparently, but in the place at which the seed layer has dissolved, the adhesion between the Cu plating film and the barrier metal film is insufficient and, thereby, a void occurs at such a place by a rapid change in stress due to the heat treatment conducted thereafter. Examples of documents in related art further includes Japanese Laid-open Patent Publication No. 2007-141927, Japanese Laid-open Patent Publication No. 2007-142236, Japanese Laid-open Patent Publication No. 2007-173511, U.S. Pat. No. 6,136,707, Japanese Laid-open Patent Publication No. 2007-281485, Japanese Laid-open Patent Publication No. 2004-111926, Japanese Laid-open Patent Publication No. 2006-24943, Japanese Laid-open Patent Publication No. 2000-91271, Japanese Laid-open Patent Publication No. 2004-153274, Japanese Laid-open Patent Publication No. 2005-51185, and Japanese Laid-open Patent Publication No. 2001-160590.